Opto-electronic devices with multiple oxide apertures

ABSTRACT

A vertical cavity apparatus includes a die with a top surface and a plurality of planar electrically conducting layers. At least one of the layers is an oxide layer formed of an oxidizable material that is oxidized upon exposure to an oxidizing agent to convert the oxidizable material to an electrical insulator. A plurality of oxide apertures are formed by via holes connecting the top surface to the oxide layer. A majority of the individual oxide apertures have different sizes. An optoelectronic device is coupled to a single oxide aperture in the die.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of Ser. No.09/603,140, filed Jun. 23, 2000, which is a continuation-in-part of Ser.No. 09/375,338, filed Aug. 16, 1999, which is a continuation of Ser. No.09/060,227, filed Apr. 14, 1998 (now U.S. Pat. No. 5,991,326), said Ser.No. 09/603,140 also being a continuation-in-part of and claiming thebenefit of provisional application Ser. No. 60/184,706 filed Feb. 24,2000, all of which applications are fully incorporated by referenceherein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates generally to a vertical cavity apparatus,and more particularly to a vertical cavity structure that includes a diewith a plurality of oxide apertures formed by via holes, trenchstructures and mesas.

[0004] 2. Description of R Art

[0005] Continued advances in long-distance, fiber-optic communicationsdepend on high-quality laser sources. Since optical fibers exhibitlowest attenuation and dispersion at the wavelengths of 1.3 μm and 1.55μm, suitable sources should emit at these relatively long wavelengths insingle-mode operation.

[0006] Traditionally, long-wavelength distributed feedback (DFB) lasersare employed in fiber-optic communications systems for their singlelongitudinal and transverse mode characteristics. However, fabricatingDFB lasers involves very complicated and low-yield processes.Furthermore, the DFB laser performance is very sensitive to thesurrounding temperature change. Thus, complicated electronics are neededin the transmitter to control the operating environment. Thesedisadvantages render the DFB laser a very expensive light source andseverely limit its application in the fiber-optic communications field.

[0007] Vertical Cavity Surface Emitting Lasers (VCSELs) emitting in the1.3 μm and 1.55 μm ranges have been visualized as promising candidatesfor replacing DFBs in telecommunications applications. Due to theirextremely short cavity length (on the order of one lasing wavelength),VCSELs are intrinsically single longitudinal mode devices. Thiseliminates the need for complicated processing steps that are requiredfor fabricating DFB lasers. Furthermore, VCSELs have the advantage ofwafer-scale fabrication and testing due to their surface-normaltopology.

[0008] Unfortunately, VCSELs suffer material limitations that arenegligible in the case of short-wavelength VCSELs but drastically affectthe performance of long-wavelength VCSELs. The small availablerefractive index difference Δn between reflective layers of theDistributed Bragg Reflectors(DBRs) requires that a large number oflayers with high composition and thickness precision be used to achievesufficient reflectivity. Another object of the present invention is toreduce loss in a vertical cavity apparatus. Due to the small An therelatively thick DBR's result in high diffraction losses. Furthermore,high free-carrier absorption loss limits the maximum achievablereflectivity and the high non-radiative recombination rate increases theelectrical current for reaching the lasing threshold.

[0009] These problems have restricted prior art fabrication efforts tonon-wafer-scale, complicated and low-yield processes such as waferfusion described by D. I. Babic et al., “Room-TemperatureContinuous-Wave Operation of 1.54 μm Vertical-Cavity-Lasers”, IEEEPhotonics Technology Letters, Vol. 7, No. 11, 1995, pp. 1225-1227 and Y.Ohiso et al., “1-55 μm Vertical-Cavity Surface-Emitting Lasers withWafer-Fused InGaAsP/InP—GaAs/AlAs DBRs”, Electronics Letters, Vol. 32,No. 16, 1996, pp. 1483-1484. Alternatively, long-wavelength VCSELs havealso been manufactured by evaporation of dielectric mirrors as describedby S. Uchiyama et al., “Low Threshold Room Temperature Continuous WaveOperation of 1.3 μm GaInAsP/InP Strained Layer Multiquantum Well SurfaceEmitting Laser”, Electronics Letters, Vol. 32, No. 11, 1996, pp.1011-13; M. A. Fisher et al., “Pulsed Electrical Operation of 1.5 μmVertical-Cavity-Surface-Emitting Lasers”, IEEE Photonics TechnologyLetters, Vol. 7, No. 6, 1995, pp. 608-610 and T. Tadokoro et al., “RoomTemperature Pulsed Operation of 1.5 μm GaInAsP/InP Vertical-CavitySurface-Emitting Lasers”, IEEE Photonics Technology Letters, Vol. 4, No.5, 1992, pp. 409-411.

[0010] Unfortunately, these methods do not allow one to efficiently growlong-wavelength VCSELs.

[0011] Tunneling in GaAs, at an n+/p+ junction, is well known (see, forexample, N. Holonyak, Jr. and I. A. Lesk, Proc. IRE 48, 1405, 1960), andis generally of interest for its negative resistance. Tunneling in GaAscan be enhanced with an InGaAs transition region (see, for example, T.A. Richard, E. I. Chen, A. R. Sugg. G. E. Hofler, and N. Holonyak, Jr.,Appl. Phys. Lett. 63, 3613, 1993), and besides its negative resistancebehavior, can be used in reverse bias as a form of “ohmic” contact. Thisallows, for example, the reversal of the doping sequence of an Al sub xGa sub 1-x As—GaAs quantum well heterostructure laser (n forward arrow pto p forward arrow n) grown on an n-type GaAs substrate. See, forexample, A. R. Sugg, E. I. Chen, T. A. Richard, S. A. Maranowski, and N.Holonyak, Jr., Appl. Phys. Lett. 62, 2510 (1993) or the cascading ofabsorbing regions to produce higher efficiency solar cells (see forexample D. L. Miller, S. W. Zehr and J. S. Harris Jr, Journ. App. Phys.,53(1), pp 744-748, (1982) and P. Basmaji, M. Guittard, A. Rudra, J. F.Carlin and P. Gibart, Journ. Appl,. Phys., 62(5), pp 2103-2106, (1987)).

[0012] A variety of devices are formed on wafers including but notlimited to lasers, photodetectors, filters electronic circuits and MEMs.These devices are formed on the wafers utilizing a variety of standardmulti-processing steps and procedures. The wafer is typically moved fromone process station to another until the final device is completed onthe wafer. The devices are then tested. Following testing, the wafer isdiced and individual devices are then mounted, electrical connectionsare made and then there is a final sealing.

[0013] This type of wafer scale manufacturing exposes the individualdevices to contaminants and corrosive elements found in the atmospherebecause of the lengthy time it takes to complete the manufacturingprocess. Corrosive elements, such as moisture and oxygen, can cause adegradation in the device that is made.

[0014] Laser diodes typically include an n-type substrate, an activelayer, a p-type clad layer and a p-type cap layer that is laminated overthe n-type substrate. In one such semiconductor laser, the n-typesubstrate is formed of AlGaAs and the active layer is formed of GaAs. Anelectrode is selectively formed on the obverse surface of the laserdiode in an opening of the p-type cap layer. A rear electrode is formedon the reverse surface of the substrate. The resulting structure is alaser diode chip more commonly known as a double heterostructure (DHstructure). This laser diode chip can be mounted on a radiation plate.The assembly is then encapsulated to hermetically seal the device.

[0015] U.S. Pat. No. 5,896,408 discloses a VCSEL with at least onemirror that includes a plurality of planar electrically conductinglayers with different indices of refraction. One of the layers includesan oxidizable material. To expose the oxidizable layer to an oxidizingagent, and convert the material to an electrical insulator, three ormore holes are etched down from the top surface of the VCSEL to thelayer containing the oxidizable material. The oxidizing agent is thenintroduced into the top of these holes. The partial oxidation of thelayer converts the layer to one having a conducting region surrounded byan electrically insulating region, the conducting region beingpositioned under the top electrode.

[0016] U.S. Pat. No. 5,978,408 discloses a VCSEL structure withwell-defined and well-controlled oxidized regions that are used todefine the lasing aperture of the VCSEL. These oxidized regions areformed by the use of a multiplicity of cavities arranged in a predefinedpattern in the laser structure. The lasing aperture is an unoxidizedregion bounded by these oxidized regions centered about the cavities.During the oxidation process, an AlGaAs layer with high aluminum contentembedded in the semiconductor structure is oxidized radially outwardsfrom each of these cavities until the oxidized regions between twoadjacent cavities overlap. However, the devices in the above-referencedpatents fail to change the pitch of individual groups of via holes toform different oxide aperture sizes There is a need for electro-opticdevices with an array of via holes, trench structures or mesas that areused to form several oxide apertures of different sizes. There is afurther need for electro-optic devices with an array of via holes,trench structures or mesas that are used to form several oxide aperturesof different sizes, with the oxide apertures coupling light from anactive region underneath and while being electrically isolated fromtheir neighbors.

SUMMARY OF THE INVENTION

[0017] Accordingly, an object of the present invention is to provideimproved electro-optic devices.

[0018] Another object of the present invention is to provide improvedmicro-optomechanical, micro-electromechanical and micro-optoelectricaldevices that are formed on a single die.

[0019] A further object of the present invention is to provideelectro-optic devices with an array of via holes to form several oxideapertures of different sizes, with the oxide apertures beingelectrically isolated from each other and coupling light from anunderneath active region.

[0020] A further object of the present invention is to provideelectro-optic devices with an array of trench structures to form severaloxide apertures of different sizes, with the oxide apertures beingelectrically isolated from each other and coupling light from anunderneath active region.

[0021] A further object of the present invention is to provideelectro-optic devices with an array of mesas to form several oxideapertures of different sizes, with the oxide apertures beingelectrically isolated from each other and coupling light from anunderneath active region.

[0022] These and other objects of the present invention are achieved ina vertical cavity apparatus. The apparatus includes a die with a topsurface and a plurality of planar electrically conducting layers. Atleast one of the layers is an oxide layer formed of an oxidizablematerial that is oxidized upon exposure to an oxidizing agent to convertthe oxidizable material to an electrical insulator. A plurality of oxideapertures are formed by via holes connecting the top surface to theoxide layer. A majority of the individual oxide apertures have differentsizes. An optoelectronic device is coupled to a single oxide aperture inthe die.

[0023] In another embodiment of the present invention, a vertical cavityapparatus includes a die with a top surface and a plurality of planarelectrically conducting layers. At least one of the layers is an oxidelayer formed of an oxidizable material that is oxidized upon exposure toan oxidizing agent to convert the oxidizable material to an electricalinsulator. A plurality of oxide apertures are formed by trenchstructures connecting the top surface to the oxide layer. A majority ofthe individual oxide apertures have different sizes. An optoelectronicdevice is coupled to a single oxide aperture in the die.

[0024] In another embodiment of the present invention, a vertical cavityapparatus includes a die with a top surface and a plurality of planarelectrically conducting layers. At least one of the layers is an oxidelayer formed of an oxidizable material that is oxidized upon exposure toan oxidizing agent to convert the oxidizable material to an electricalinsulator. A plurality of oxide apertures are formed by mesas connectingthe top surface to the oxide layer. A majority of the individual oxideapertures have different sizes. An optoelectronic device is coupled to asingle oxide aperture in the die.

[0025] In another embodiment of the present invention, a multi modedevice, includes a die with a top surface and a plurality of layers. Atleast one of the layers is an oxide layer formed of an oxidizablematerial that is oxidized upon exposure to an oxidizing agent to convertthe oxidizable material to an electrical insulator. The die includes aplurality of via holes/trenches/mesas connecting the top surface to theoxide layer. A majority of the individual oxide apertures havingdifferent size. A tunable laser is coupled to a single oxide aperture inthe die. The tunable laser includes, a semiconductor active regionpositioned between upper and lower confining regions of opposite typesemiconductor material, and first and second reflective memberspositioned at opposing edges of the active and confining regions. Thelaser produces an output beam.

[0026] In another embodiment of the present invention, an optical systemincludes a die with a top surface and a plurality of layers. At leastone of the layers is an oxide layer formed of an oxidizable materialthat is oxidized upon exposure to an oxidizing agent to convert theoxidizable material to an electrical insulator, the die including aplurality of via holes/trenches/mesas connecting the top surface to theoxide layer. A majority of individual oxide apertures having differentzes. A tunable laser is formed in one of the oxide apertures. The laserincludes an active region with first and second opposing reflectors thatdefine a laser gain vity. A first photodetector is positioned outside ofthe laser gain cavity. An adjustable wavelength selective filter isincludes and splits the output beam into a transmitted portion and areflected portion. The adjustable wavelength selective filter ispositioned at an angle 0 relative to the optical axis to provide anangular dependence of a wavelength reflection of the wavelengthselective filter and direct the reflected output beam towards the firstphotodetector. The wavelength selective filter provides wavelengthselectivity by changing the angle θ and a ratio of the transmitted andreflected portions is a function of wavelength of output beam and theangle θ.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1(a) is a cross-sectional view of a VCSEL structure of thepresent invention with two active layers, a tunnel junction positionedbetween the top and bottom mirrors and an oxide layer positioned betweenthe top mirror and the top active layer.

[0028]FIG. 1(b) is a cross-sectional view of a VCSEL structure of thepresent invention with a tunnel junction positioned between the top andbottom mirrors and an oxide layer positioned adjacent to the bottommirror.

[0029]FIG. 1(c) is a cross-sectional view of the VCSEL structure of FIG.1(a) with a second tunnel positioned between the top and bottom mirrors.

[0030]FIG. 2 is a cross-sectional view of the VCSEL structure of FIG.1(a) with three active layers, two tunnel junctions and an oxide layerpositioned between the top mirror and the top active layer.

[0031]FIG. 3 is a cross-sectional view of the VCSEL structure of FIG. 2with two additional oxide layers, each positioned between a tunneljunction and an active layer.

[0032]FIG. 4 is a cross-sectional view of the VCSEL structure of FIG. 2two partial DBR's, each positioned between a tunnel junction and anactive layer.

[0033]FIG. 5 is a cross-sectional view of the VCSEL structure of FIG. 4with two additional oxide layers, each positioned between a tunneljunction and an active layer.

[0034]FIG. 6 is a perspective view of the substrate from the FIG. 1(a)through FIG. 5 VCSELs with an etched pattern formed on a top or bottomsurface.

[0035]FIG. 7 is a cross-sectional view of a top mirror used with thepresent invention that includes a metallic layer.

[0036]FIG. 8 is a cross-sectional view of a top mirror used with thepresent invention that is coupled to a tunable filter.

[0037]FIG. 9 is a cross-sectional view of a tunnel junction used withthe present invention, illustrating the tunnel junction's opposing firstand second sides.

[0038]FIG. 10 is a cross-sectional view of an active layer of thepresent invention that includes quantum wells and barriers.

[0039]FIG. 11 is a cross-sectional view of a VCSEL structure of thepresent invention with a tunnel junction positioned between the topmirror and an oxide layer, and the top mirror is an n-doped DBR.

[0040]FIG. 12 is a cross-sectional view of a VCSEL structure of thepresent invention with a tunnel junction positioned between the topmirror and an oxide layer, and the top mirror is an nid DBR.

[0041]FIG. 13 is a cross-sectional view of a VCSEL structure of thepresent invention with an oxide layer positioned between the top mirrorand the top active layer, and a tunnel junction positioned between theoxide layer and the top active layer.

[0042]FIG. 14 is a cross-sectional view of a VCSEL structure of thepresent invention with an ion implantation layer.

[0043]FIG. 15 is a cross-sectional view of a VCSEL structure similar tothe VCSEL structure of FIG. 5 with ion implantation layers substitutedfor the second and third oxide layers.

[0044]FIG. 16 a cross-sectional view of a VCSEL structure similar to theVCSEL structure of FIG. 1(a) with the inclusion of an etched layer.

[0045]FIG. 17 is a cross-sectional view of a VCSEL structure similar tothe VCSEL structure of FIG. 5 with etched layers substituted for thesecond and third oxide layers.

[0046]FIG. 18(a) is a cross-sectional view of the etched layer of FIG.16 with a vertical profile.

[0047]FIG. 18(b) is a cross-sectional view of the etched layer of FIG.16 with a slopped profile

[0048]FIG. 18(c) is a cross-sectional view of the etched layer of FIG.16 with a variable geometric profile.

[0049]FIG. 18(d) is a cross-sectional view of the etched layer of FIG.16 with another example of a variable geometric profile.

[0050]FIG. 18(e) is a cross-sectional view of the etched layer of FIG.16 with yet another example of a variable geometric profile.

[0051]FIG. 19 is a cross-sectional view of a vertical cavity structureof the present invention with a fiber grating.

[0052]FIG. 20 is a cross-sectional view of a top mirror used with thepresent invention that is a fused mirror.

[0053]FIG. 21 is a cross-sectional view of a top mirror used with thepresent invention that is a cantilever structure.

[0054]FIG. 22(a) is a sectional view of one embodiment of a verticalcavity structure of the present invention that includes a die with aplurality of oxide apertures formed by via holes.

[0055]FIG. 22(b) is a top down view of the FIG. 26(a) structure.

[0056]FIG. 23 is a top down view of an opto electronic device of thepresent invention illustrating etching trench structures around mesas.

[0057]FIG. 24 is a top down view of a DBR of the present inventionillustrating four devices of different aperture sizes on one die.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0058] One embodiment of the present invention is a communicationapparatus with a plurality of oxide apertures formed in a single die.The die has a plurality of layers, one of which is an oxide layer. Theplurality of oxide apertures are formed by via holes, trench structuresand mesas connecting a top surface of the die to the oxide layer. Amajority of the individual oxide apertures have different pitches.

[0059] An optoelectronic device is coupled to a single oxide aperture inthe die. Suitable optoelectronic devices include but are not limited toa vertical cavity or non-vertical cavity, surface emitting laser,detector, filter, pin detector, avalanche photodiode, LED, Resonantcavity LED, modulator, attenuator, amplifier, SOA, ring waveguide, ringwaveguide oscillator micromechanical structure, micromechanicalstructure with a single support member, micromechanical structure withat least two support members and tunable micromechanical structure.

[0060] For purposes of this specification, vertical cavity apparatus isgenerally denoted as 10 and is not limited to a VCSEL. As illustrated inFIGS. 1(a) and 1(b), vertical cavity structure is a VCSEL 10. VCSEL 10is a layered structure with top and bottom mirrors 12 and 14. Light isemitted in a vertical direction that is perpendicular to the planes ofthe layers. Top and bottom mirrors 12 and 14 are preferably DBR's. Theuse of DBR's allows to obtain very high reflectivities (>99.5%).

[0061] First and second active layers 16 and 18 are positioned betweentop and bottom mirrors 12 and 14. Examples of suitable materials forfirst and second active layers 16 and 18 include but are not limited toInGaAsP, InAlGaAs, InGaAs and the like. At least one tunnel junction 20and a first oxide layer 22 are each positioned between top and bottommirrors 12 and 14. Tunnel junction 22 can have a width in the range of 5nm-500 nm. Oxide layer 22 can a thickness of less than 0.5 μm. Alsoincluded is a substrate 24. Substrate 24 can be made of a variety ofmaterials including but not limited to InP, GaAs and the like. In FIG.1(a), first oxide layer 22 is positioned between top mirror 12 and firstactive layer 16. In FIG. 1(b), first oxide layer 22 is positionedbetween bottom mirror 14 and second active layer 18. Oxide layer 22 islocated in a p type material. There are two main advantages depending onthe position of tunnel junction 20. When positioned between two activeregions tunnel junction 20 increases the gain. When positioned on top ofan active region tunnel junction 20 allows low intracavity accessresistance and use of low loss mirrors by either using n-doped DBR (forvertical injection) or undoped DBR (intracavity contact) which have lessfree carrier losses than p-type DBRs.

[0062] Top mirror 12 can be partially oxidized. Oxidation of top mirror12 creates a large refractive index difference between adjacent layers.This index difference can drastically increase the stop bandwidth of topmirror 12, and therefore relax the growth accuracy for top mirror 12.The high-contrast, oxidized top mirror 12 reduces the diffraction lossand eliminates the free-carrier-absorption loss.

[0063] When top mirror 12 is oxidized, the thickness of high Al-contentlayers is calculated by taking into account the refractive index andthickness change resulted from the oxidation process. The oxidized partof top mirror 12 is undoped to eliminate free-carrier absorption loss.Oxidation of top mirror 12 can be done in conjunction with the oxidationof the confinement layer. The oxidation process can be conducted in awater-saturated nitrogen ambient, at a temperature between 350° C. to450° C.

[0064] Top and bottom mirrors 12 and 14, as well as the active regionscan be grown in the same epitaxial process. This procedure allowsfull-wafer growth and processing, and therefore significantly reducesthe cost of fabricating long-wavelength VCSELs. The lattice relaxedportion of VCSEL 10 can also be grown by a separate epitaxial growthprocess. When using the molecular beam epitaxy method, the growthtemperature for top mirror 12 is preferably less than 500° C. Thelattice relaxed mirror can incorporate a tunnel junction. At least onelayer of VCSEL 10 can be grown while the substrate 24 is held stationaryand the other layers are grown while substrate 24 is rotated.

[0065] Referring now to FIG. 1(c), a second tunnel junction 26 can beoptionally included and positioned between bottom mirror 14 and secondactive layer 18. Additional tunnel junctions increase the gain. A firstpartial DBR 28 can also be included and positioned between first andsecond active regions 16 and 18.

[0066]FIG. 2 illustrates an embodiment of VCSEL 10 with a third activeregion 30. First and second tunnel junctions 20 and 26 are positionedbetween first, second and third active regions 16, 18 and 30respectively. Although first oxide layer 22 is shown as being positionedadjacent to top mirror 12, it will be appreciated that another oxidelayer 22 can alternatively be positioned between active layers.Additional active layers can be included. Preferably, no more than tenactive layers are included. More preferably the number of active layersis five or less or no more than three.

[0067] Additional oxide layers can be included. FIG. 3 the inclusion ofsecond and a third oxide layers 32 and 34 are used to reduce currentspread. Oxide layers 32 and 34 become insulators and force the currentto be funneled in the semiconductor layer (at the center) that is notoxidized. In the embodiment illustrated in FIG. 3, second oxide layer 32is positioned between first tunnel junction 20 and second active layer18, and third oxide layer 34 is positioned between second junction 26and third active region 30. This specific arrangement reduces thecurrent spreading between active layers.

[0068] As shown in FIG. 4, multiple partial DBR's can be included andpositioned between top and bottom mirrors 12 and 14. First and secondpartial DBR's 28 and 36 form several FP cavities with different FPwavelengths in order to stabilize the performance in temperature and thewavelength range of tuning. In FIG. 4, first partial DBR 28 ispositioned between first and second active regions 16 and 18. Secondpartial DBR 36 is positioned between second and third active regions 18and 30. In the embodiment illustrated in FIG. 4, first tunnel junction20 is positioned first active region 16 and first partial DBR 28. Secondtunnel junction 26 is positioned between second active region 18 andsecond partial DBR 36.

[0069] As illustrated in FIG. 5, the VCSEL 10 from FIG. 4 can alsoinclude second and third oxide layers 32 and 34 that are positionedbetween the first and second partial DBR's 28 and 36 and active regions18 and 30.

[0070] Substrate 24 has a given crystallographic orientation. Examplesof suitable crystallographic orientations include but are not limited to(001), (311A), (311B) and (110). As illustrated in FIG. 6, substrate 24can have an etched pattern 38 formed on a top or bottom surface, wherethe top surface is adjacent to bottom mirror 14. Substrate 24 caninclude a dielectric pattern. All or a portion of the substrate 24layers can be grown using selective area epitaxy.

[0071] Top mirror 12 can be tunable. A metallic layer 40 can bepositioned on the top of top mirror 12. Metallic layer 40 boosts thereflectivity of the DBR. Top mirror 12 can be integrated with a tunablefilter 42 (FIG. 8).

[0072] Referring now to FIG. 9, tunnel junctions 20 and 26 have firstand second opposing sides 44 and 46 which are cladding regions. Claddingregions 44 and 46 can be made of the same material, different materials,have different thickness and have different doping profiles and can benon doped. Tunnel junctions 20 and 26 can be uniformly doped andnon-uniformly doped. Tunnel junctions 20 and 26 are doped with oppositedopants (i.e., n-type/p-type). Additionally, tunnel junctions 20 and 26and cladding regions 44 and 46 can be compositionally graded.

[0073] As illustrated in FIG. 10 each active region 16, 18 and 30includes a least one quantum well, generally denoted as 48 in FIG. 10.In one embodiment, each active region includes a plurality of quantumwells 48. The quantum wells 48 in each active region 16, 18 and 30 canhave different widths, the same widths, different maximum gainwavelengths, the same maximum gain wavelength, different compositions,the same strain and different strain. Quantum wells 48 can be strainedquantum wells, tensile strained quantum wells, unstrained quantum wells,compression strained quantum well. All quantum wells 48 can be the sametype, different types and combinations.

[0074] All or some of the different quantum wells 48 in each activeregion 16, 18 and 30 can have different widths, generate differentmaximum gain wavelengths, or generate the same maximum gain wavelengths.In one embodiment, quantum wells 48 in active region 16 generate a firstwavelength, those in active region 18 a different wavelength, those inactive region 30 yet another wavelength and so on.

[0075] Referring still to FIG. 11, the plurality of quantum wells 48 ineach active region 16, 18 and 30 can have a plurality of barriers 50.All or a portion of the plurality of barriers 50 can have the samestrain or different strains.

[0076] Each active region 16, 18 and 30 can be a bulk region. The use ofa bulk region increases the confinement factor and the modal gain. Bulkregions 52 can be non-doped, uniformly doped or non-uniformly doped.Bulk regions 52 have opposing first and second sides 54 and 56respectively that can be made of the same material or differentmaterials. The thickness of first and second sides 54 and 56 can be thesame or different. First and second sides 54 and 56 can have the samedoping profiles, different doping profiles and different widths. Eachbulk region 52 can be compositionally graded.

[0077] Due to the higher mobility of electrons compared to holes,reverse biasing enables the injection of holes through a low resistive nregion. This is achieved by using an n doped top mirror 12 or using thestructures of FIGS. 11 and 12. The structure illustrated in FIG. 11includes an n doped top DBR 12 that reduces the resistance of the entireVCSEL 10 structure. In this embodiment, tunnel junction 20 allows thecurrent to be injected with a low access resistance than oxide layer 22which is located in p-regions.

[0078] In FIG. 12 first tunnel junction 20 is positioned between topmirror 12 and first oxide layer 22 and is either partially doped orundoped The contact taken laterally on top of tunnel junction 20 cantherefore flow in the low resistive n-type material before beingconverted into holes through the reverse biased tunnel junction 20. Thecurrent is then funneled through the oxide aperture in layer 22. In theFIG. 11 embodiment, the current is injected through the top DBR 12 whilein FIG. 12 embodiment the current is injected laterally. With the FIG.12 embodiment, lateral injection of current permits the use of anon-doped DBR which greatly reduces the free carrier losses.

[0079] In another embodiment, illustrated in FIG. 13, first oxide layer22 is positioned between top mirror 12 and first tunnel junction 20. Inthis embodiment, first oxide layer 22 is used for index guiding to allowfor single mode stability and tunnel junction 20 function is used forcurrent injection through low optical losses materials. In thisembodiment, the current confinement is done through an implantationstep, plasma etching or undercutting.

[0080] Variations of embodiments illustrated in FIGS. 11, 12 and 13include use of a double intracavity contact by putting a lateral contactbelow active region 16 to allow bottom DBR 14 to be undoped whichreduces the losses due to bottom DBR 14. Additionally, the embodimentsillustrated in FIGS. 1 through 14 can also employ the lateral injectionof current shown in the FIG. 11 and 12 embodiments.

[0081] Top mirror 12 can be an n-doped DBR. In order to benefit from thelow access resistance of n-doped DBR 12 an injection through a reversebiased tunnel junction 20 are combined with first oxide layer 22 thatinduces an index guiding. In another embodiment of the presentinvention, illustrated in FIG. 14, VCSEL 10 includes first tunneljunction 20 and an ion implantation layer 58, each positioned betweentop and bottom mirrors 12 and 14. Ion implantation is used to locallydestroy the conductive properties which enables the creation of alocally conductive area and provides for current localization. In theembodiment illustrated in FIG. 14, first ion implantation layers 58 issubstituted for the oxide layers of the FIG. 1 through 13 embodiments.Additional ion implantation layers can be included and be positionedbetween adjacent tunnel junctions and active regions as shown in FIG.15. First oxide layer 22 can also be included and positioned between topmirror 12 and top active region, or between bottom mirror 14 and thebottom active region (not shown). In the FIG. 15 embodiment, there is anamount of index guiding and current confinement.

[0082] In the FIG. 15 embodiment, the layers are grown by standardmethods, such as molecular beam epitaxy and the like. After this growtha photoresist mask is deposited above the parts where the implantationneeds to be prevented. The structure is then exposed to a high energyion beam. Ions are implanted to depths which are determined by the ionbeam energy.

[0083] In another embodiment, illustrated in FIG. 16, VCSEL 10 includesfirst tunnel junction 20 and a first etched layer 60, each positionedbetween top and bottom mirrors 12 and 14. In the embodiment illustratedin FIG. 16, first etched layer 60 is substituted for the oxide layers ofthe FIGS. 1 through 13 embodiments. Additional etched layers can beincluded and be positioned between adjacent tunnel junctions and activeregions as shown in FIG. 17. Etching provides formation of currentlocalization because etched portions are electrical insulators.

[0084] Each etched layer 60 can have a variety of different profiles. Asillustrated in FIGS. 18(a), 18(b), 18(c) through 18(e), etched layer 60can have with respect to a longitudinal axis of substrate 24, a verticalprofile, a slopped profile, a variable geometric profile and an undercutprofile.

[0085] One or both of top mirror 12 and bottom mirror 14 can be alattice relaxed mirror. First tunnel junction 20 is positioned betweentop and bottom mirrors 12 and 14. Additionally, first oxide layer 22 canbe positioned adjacent to top mirror 12 or bottom mirror 14. With any ofthe embodiments illustrated in FIGS. 1 through 17 top and bottom mirrors12 and 14 can be lattice relaxed mirrors. Lattice relaxed mirrors permitthe use of materials with high index contrast, high reflectivities, andlow thermal resistively without the constraint of lattice matching.

[0086] In this embodiment, substrate 24 can be made of a latticedefining material such as InP, GaAs and the like. A stack of layers ontop of substrate 24 forms bottom mirror 14 and can consist of acombination of material such as InAlGaAs/InAlAs, InGaAsP/InP,AlGaAsSb/AlAsSb, InGaN, GaN, AlGaInAsN/GaAs and the like. Bottom mirror14 can be formed of alternating layers of InAlGaAs and InAlAs. Therefractive index is different between the layers. The number of thealternating layers can be, for example, from 2-2000 in order to achievethe desired reflectivity.

[0087] Bottom mirror 14 can be lattice matched to the lattice definingmaterial of substrate 24. Bottom 14 can be grown using any epitaxialgrowth method, such as metal-organic chemical vapor deposition (MOCVD),molecular beam epitaxy (MBE) e-beam, chemical beam epitaxy, and thelike.

[0088] A spacer layer, not shown, can be deposited on top of bottommirror 14. The material of spacer layer can be made of InAlGaAs/InAIAs,InGaAsP/InP, AlGaAsSb/AlAsSb, InGaN, GaN, AlGaInAsN/GaAs and the like.The spacer layer can be lattice matched to the lattice defining materialof substrate 24.

[0089] Top mirror 12 can also be a DBR that is grown on top of aconfinement layer that can also be considered as part of top mirror 12.The confinement layer and top mirror 12 can be the lattice relaxedportion of VCSEL 10. The lattice mismatch factor may be 0-500%, from thelattice defining material.

[0090] Top mirror 12 is made of a material such as AlGaAs, InGaP,InGaAsP and the like. In one embodiment, top mirror 12 is made of a setof alternating layers of AlGaAs and GaAs. The high Al-content AlGaAslayers are the low refractive index layers.

[0091] In another embodiment, one or both of top mirror 12 and bottommirror 14 can be a dielectric mirror. First tunnel junction 20 ispositioned between top and bottom mirrors 12 and 14. First oxide layer22 can be positioned adjacent to top mirror 12 or bottom mirror 14. Withany of the embodiments illustrated in FIGS. 1 through 17 top and bottommirrors 12 and 14 can be dielectric mirrors. Dielectric materialsexhibit large index contrast. Therefore a fewer number of pairs isnecessary to obtain high reflectivities.

[0092] Referring now to FIG. 19, one or both of mirrors 12 and 14 can bea fiber 62 with a grating 64. Suitable fibers 62 include but are notlimited to single or multi-mode filters, silicon, plastic and the like.First tunnel junction 20 is positioned between top and bottom mirrors 12and 14. First oxide layer 22 can be positioned adjacent to top mirror 12or bottom mirror 14. With any of the embodiments illustrated in FIGS. 1through 17 top and bottom mirrors 12 and 14 can be a fiber 62 withgrating 64. Grating 64 can be used to form an external cavity whichallows for wavelength tuning by moving fiber 62. Grating 64 alsoeliminates the need for DBR's and therefore reduces manufacturing timeand costs.

[0093] In another embodiment, illustrated in FIG. 20, one or both of topand bottom mirrors 12 and 14 is a fused mirror. Wafer fusion has thesame advantages as growth of lattice relaxed mirror except that in thewafer fusion case no threading dislocations are present in the mirror.The use of wafer fusion permits the use of a material system for the DBRthat is mismatched from the substrate.

[0094] First tunnel junction 20 is positioned between top and bottommirrors 12 and 14. First oxide layer 22 can be positioned adjacent totop mirror 12 or bottom mirror 14. With any of the embodimentsillustrated in FIGS. 1 through 17 top and bottom mirrors 12 and 14 canbe fused mirrors.

[0095] As illustrated in FIG. 21, top mirror 12 of any of the FIGS. 1through 20 can be a cantilever apparatus that uses an electrostaticforce that pulls on a cantilever arm. The mechanical deflectionresulting from this electrostatic force is used to change the length ofa Fabry-Perot microcavity and consequently to the resonance wavelength.

[0096] In this embodiment, top mirror 12 has a cantilever structureconsisting of a base 66, an arm 68 and an active head 70. The bulk ofcantilever structure may consist of a plurality of reflective layers 72which form a distributed Bragg reflector (DBR). Layers 72 can be formedof different materials including but not limited to AlGaAs. Differentcompositional ratios are used for individual layers 72, e.g., Al_(0.09)Ga_(0.91) As/Al_(0.58) Ga_(0.42) As. The topmost layer of layers 72 isheavily doped to ensure good contact with an electrical tuning contact74 deposited on top of the cantilever structure.

[0097] The actual number of layers 72 may vary from 1 to 20 and more,depending on the desired reflectivity of the DBR. Furthermore, anysuitable reflecting material other than AlGaAs may be used to producelayers 72. Active head 70 is made of layers. However, arm 68 and base 66do not need to be made of layers.

[0098] Base 66 can have a variety of different geometric configurationsand large enough to maintain dimensional stability of the cantileverstructure. The width of arm 68 ranges typically from 2 to 8 micronswhile its length is 25 to 100 mu m or more. The stiffness of arm 68increases as its length decreases. Consequently, shorter cantileversrequire greater forces to achieve bending but shorter cantilevers alsoresonate at a higher frequency. The preferred diameter of active head 70falls between 5 and 40 microns. Other dimensions are suitable.

[0099] Electrical tuning contact 74 resides on all or only a portion ofa top of the cantilever structure. Electrical tuning contact 74 besufficiently large to allow application of a first tuning voltageV_(t1). A support 76 rests on a substrate 78 across which a voltage canbe sustained. Substrate 78 can include a second DBR 68. Support 76 canbe made of the same material as layers 72. A voltage difference betweenlayers 72 and substrate 78 causes a deflection of arm 68 towardssubstrate 78. If layers 72 and substrate 78 are oppositely doped, then areverse bias voltage can be established between them. Substrate 78 issufficiently thick to provide mechanical stability to the entirecantilever apparatus. Inside substrate 78 and directly under active head70 are one or more sets of reflective layers with each set forming asecond DBR. A more complete description of the cantilever apparatus isdisclosed in U.S. Pat. No. 5,629,951, incorporated herein by reference.

[0100] Referring now to FIGS. 22(a) and 22(b), one embodiment of thepresent invention is a vertical cavity or non-vertical cavity structure10, with an oxide layer, that includes a die 80 with a top surface 82and a plurality of planar electrically conducting layers, generallydenoted as 84. At least one of the layers 84 is an oxide layer 22. Oxidelayer 22 is formed of an oxidizable material that is oxidized uponexposure to an oxidizing agent to convert the oxidizable material to anelectrical insulator. A plurality of oxide apertures 86 are formed byvia holes, trench structures and mesas FIG. 23. In FIG. 23, the mesashave sizes of 40 μm, 39 μm, 37 μm, and 38 μm respectively. Oxideapertures 86 connect top surface 82 to oxide layer 22. In oneembodiment, a majority of individual via holes 22 have differentpitches. For purposes of this specification, pitch is the distancebetween any two cross via holes, as illustrated in FIG. 24. In anotherembodiment, all of oxide apertures 22 have different pitches.

[0101] An optoelectronic device 10 is coupled to only one of the oxideapertures 86. An optoelectronic device is coupled to a single oxideaperture in the die. Suitable optoelectronic devices include but are notlimited to a vertical cavity or non-vertical cavity, surface emittinglaser, detector, filter, pin detector, avalanche photodiode, LED,Resonant cavity LED, modulator, attenuator, amplifier, SOA, ringwaveguide, ring waveguide oscillator micromechanical structure,micromechanical structure with a single support member, micromechanicalstructure with at least two support members and tunable micromechanicalstructure.

[0102] Oxide apertures 86 are etched into top surface 82 of die 80 toprovide access to oxide layer 22. Any number of oxide apertures 86 areformed, preferably the number is 3 to 4. Oxide apertures 86 extend fromtop surface 82 to at least oxide layer 22 When die 80 is exposed tosteam, the steam enters from previously formed via holes, trenchstructures and mesas and a moving oxidation front is set up. The viaholes, trench structures and mesas can be formed by photolithography todefine an etch mask, followed by dry or wet etching. The front proceedsradially from the via holes, trench structures and mesas. The process isallowed to continue until the fronts merge leaving oxidized apertures 86The shape of the via holes, trench structures and mesas, and hence oxideapertures 86 can be set by conventional photolithographic techniques.The etching of the via holes, trench structures and mesas can beperformed with a 1:5:15 mixture of phosphoric acid (H₃PO₄), hydrogenperoxide (H₂O₂) and water (H₂O). Alternatively, dry etching by reactiveion etching may be used to provide better accuracy and more verticalsidewalls.

[0103] An example of one embodiment of the present invention as follows.At 400 degrees, the oxidation rate of an AlAs VCSEL is about 2.65micrometers/min average, but varies from 2.52 to 2.74 um/min from run torun. On a 1 cm by 1 cm section size of wafer, the oxidation rate canvary by 5% due to defects and processing caused contaminations. Theoxidation rate variation translates into final oxide aperture sizedifference in the order of micrometers. For example, if the oxidationtime is constant for 22 minutes, the size of oxide aperture 86 can varyfrom 5 um to 15 um for a 125 um square mesa from run to run. If theoxidation time is kept at 11 minutes, oxide aperture 86 can could varyfrom 5 to 10 um for a 65 um square mesa. From these oxidation ratevariations, the yield for achieving single mode yield in oxide confinedVCSEL devices is very low in manufacturing, by using a fixed size mesaor a via hole array of single pitch, since the optimum oxide aperturesize for single mode operation should be less than 6 um. If oxideaperture 86 is larger than that, the VCSEL starts to operate inmulti-mode. By using the multi via hole pattern method of the presentinvention, the yield for single mode devices is increased significantlyby a factor of n, where n is the number of arrays in the via pattern Theforegoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope ofthe invention be defined by the following claims and their equivalents.

What is claimed is:
 1. A vertical cavity apparatus, comprising: a dieincluding a top surface and a plurality of planar electricallyconducting layers, at least one of the layers being an oxide layerformed of an oxidizable material that is oxidized upon exposure to anoxidizing agent to convert the oxidizable material to an electricalinsulator; a plurality of oxide apertures formed by via holes connectingthe top surface to the oxide layer, a majority of individual oxideapertures having different sizes; and an optoelectronic device coupledto a single oxide aperture in the die.
 2. The apparatus of claim 1 ,wherein the plurality includes at least two oxide apertures.
 3. Theapparatus of claim 1 , wherein the plurality includes at least threeoxide apertures.
 4. The apparatus of claim 1 , wherein the plurality ofoxide apertures are formed from a plurality of via holes that createindividual oxide apertures, wherein a distance between any pair of viaholes in one group is different from a distance between another pair ofvia holes in another group.
 5. The apparatus of claim 1 , wherein thedevice is a VCSEL.
 6. The apparatus of claim 1 , wherein the device is adetector.
 7. The apparatus of claim 1 , wherein the device is a filter.8. The apparatus of claim 1 , wherein the device is a pin detector. 9.The apparatus of claim 1 , wherein the device is an avalanchephotodiode.
 10. The apparatus of claim 1 , wherein the device is a LED.11. The apparatus of claim 1 , wherein the device is a Resonant cavityLED.
 12. The apparatus of claim 1 , wherein the device is an amplifier.13. The apparatus of claim 1 , wherein the device is an SOA.
 14. Theapparatus of claim 1 , wherein the device is a tunable vertical cavitylaser.
 15. The apparatus of claim 1 , wherein the device is a ringwaveguide.
 16. The apparatus of claim 1 , wherein the device is a ridgewaveguide.
 17. The apparatus of claim 1 , wherein the device is a ringwaveguide resonator.
 18. The apparatus of claim 1 , wherein theoxidizable material includes an Al containing III-V compound.
 19. Theapparatus of claim 1 , wherein the oxidizable material includes Al GaAs.
 20. The apparatus of claim 1 , wherein the oxidizable materialincludes In Ga As.
 21. The apparatus of claim 1 , wherein the oxidizingagent includes water.
 22. The apparatus of claim 1 , wherein theoptoelectronic device is a single mode device.
 23. A vertical cavityapparatus, comprising: a die including a top surface and a plurality ofplanar electrically conducting layers, at least one of the layers beingan oxide layer formed of an oxidizable material that is oxidized uponexposure to an oxidizing agent to convert the oxidizable material to anelectrical insulator; a plurality of oxide apertures formed by trenchstructures connecting the top surface to the oxide layer, a majority ofindividual oxide apertures having different sizes; and an optoelectronicdevice coupled to a single oxide aperture in the die.
 24. The apparatusof claim 23 , wherein the plurality includes at least two oxideapertures.
 25. The apparatus of claim 23 , wherein the pluralityincludes at least three oxide apertures.
 26. The apparatus of claim 23 ,wherein the plurality of oxide apertures are formed from a plurality oftrench structures that create individual oxide apertures, wherein thesize of one oxide aperture is different from that of another oxideaperture.
 27. The apparatus of claim 23 , wherein the device is a VCSEL.28. The apparatus of claim 23 , wherein the device is a detector. 29.The apparatus of claim 23 , wherein the device is a filter.
 30. Theapparatus of claim 23 , wherein the device is a pin detector.
 31. Theapparatus of claim 23 , wherein the device is an avalanche photodiode.32. The apparatus of claim 23 , wherein the device is a LED.
 33. Theapparatus of claim 23 , wherein the device is a Resonant cavity LED. 34.The apparatus of claim 23 , wherein the device is an amplifier.
 35. Theapparatus of claim 23 , wherein the device is an SOA.
 36. The apparatusof claim 23 , wherein the device is a tunable vertical cavity laser. 37.The apparatus of claim 23 , wherein the device is a ring waveguide. 38.The apparatus of claim 23 , wherein the device is a ridge waveguide. 39.The apparatus of claim 23 , wherein the device is a ring waveguideresonator.
 40. The apparatus of claim 23 , wherein the oxidizablematerial includes an Al containing II-V compound.
 41. The apparatus ofclaim 23 , wherein the oxidizable material includes Al Ga As.
 42. Theapparatus of claim 23 , wherein the oxidizable material includes In GaAs.
 43. The apparatus of claim 23 , wherein the oxidizing agent includeswater.
 44. The apparatus of claim 23 , wherein the optoelectronic deviceis a single mode device.
 45. A vertical cavity apparatus, comprising: adie including a top surface and a plurality of planar electricallyconducting layers, at least one of the layers being an oxide layerformed of an oxidizable material that is oxidized upon exposure to anoxidizing agent to convert the oxidizable material to an electricalinsulator; a plurality of oxide apertures formed by mesas connecting thetop surface to the oxide layer, a majority of individual oxide apertureshaving different sizes; and an optoelectronic device coupled to a singleoxide aperture in the die.
 46. The apparatus of claim 45 , wherein theplurality includes at least two oxide apertures.
 47. The apparatus ofclaim 45 , wherein the plurality includes at least three oxideapertures.
 48. The apparatus of claim 45 , wherein the plurality ofoxide apertures are formed from a plurality of mesas that createindividual oxide apertures, wherein one mesa size is different fromother mesa sizes.
 49. The apparatus of claim 45 , wherein the device isa VCSEL.
 50. The apparatus of claim 45 , wherein the device is adetector.
 51. The apparatus of claim 45 , wherein the device is afilter.
 52. The apparatus of claim 45 , wherein the device is a pindetector.
 53. The apparatus of claim 45 , wherein the device is anavalanche photodiode.
 54. The apparatus of claim 45 , wherein the deviceis a LED.
 55. The apparatus of claim 45 , wherein the device is aResonant cavity LED.
 56. The apparatus of claim 45 , wherein the deviceis an amplifier.
 57. The apparatus of claim 45 , wherein the device isan SOA.
 58. The apparatus of claim 45 , wherein the device is a tunablevertical cavity laser.
 59. The apparatus of claim 45 , wherein thedevice is a ring waveguide.
 60. The apparatus of claim 45 , wherein thedevice is a ridge waveguide.
 61. The apparatus of claim 45 , wherein thedevice is a ring waveguide resonator.
 62. The apparatus of claim 45 ,wherein the oxidizable material includes an Al containing II-V compound.63. The apparatus of claim 45 , wherein the oxidizable material includesAl Ga As.
 64. The apparatus of claim 45 , wherein the oxidizablematerial includes In Ga As.
 65. The apparatus of claim 45 , wherein theoxidizing agent includes water.
 66. The apparatus of claim 45 , whereinthe optoelectronic device is a single mode device.
 67. A multi-modedevice, comprising: a die including a top surface and a plurality oflayers, at least one of the layers being an oxide layer formed of anoxidizable material that is oxidized upon exposure to an oxidizing agentto convert the oxidizable material to an electrical insulator, the dieincluding a plurality of oxide apertures connecting the top surface tothe oxide layer, a majority of individual oxide apertures havingdifferent sizes; a tunable laser coupled to a single oxide aperture inthe die, the tunable laser including, a semiconductor active regionpositioned between upper and lower confining regions of opposite typesemiconductor material, and first and second reflective memberspositioned at opposing edges of the active and confining regions, thelaser producing an output beam.
 68. The device of claim 67 , wherein theplurality includes at least two oxide apertures.
 69. The device of claim67 , wherein the plurality includes at least three oxide apertures. 70.The device of claim 67 , the plurality of oxide apertures are formedfrom a plurality of via holes that create individual oxide apertures,wherein a distance between any pair via holes in one group is differentfrom a distance between another pair of via holes in another group. 71.The device of claim 67 , wherein the plurality of oxide apertures areformed from a first plurality of trench structures that createindividual oxide apertures, wherein the size of one oxide aperture isdifferent from the sizes of any other oxide apertures.
 72. The device ofclaim 67 , wherein the plurality of oxide apertures are formed from afirst plurality of mesas that create individual oxide apertures, whereina distance between any pair of oxide apertures is different from adistance between another pair of oxide apertures.
 73. The device ofclaim 67 , wherein the plurality of oxide apertures are formed by viaholes connecting the top surface to the oxide layer.
 74. The device ofclaim 67 , wherein the plurality of oxide apertures are formed by trenchstructures connecting the top surface to the oxide layer.
 75. The deviceof claim 67 , wherein the plurality of oxide apertures are formed bymesas connecting the top surface to the oxide layer.
 76. The device ofclaim 67 , wherein the tunable laser is a VCSEL laser.
 77. The device ofclaim 67 , further comprising: a wavelength tuning member coupled to thelaser; a wavelength measurement member positioned to receive at least aportion of the output beam of the laser, the wavelength measurementmember being coupled to the control loop; and a control loop coupled tothe wavelength measurement and the tuning member, wherein in response toa detected change in wavelength the control loop sends an adjustmentsignal to the tuning member and the tuning member adjusts a voltage orcurrent supplied to the laser to provide a controlled frequency andpower of an output beam.
 78. The device of claim 67 , wherein each ofthe top and bottom reflectors is a DBR.
 79. The device of claim 67 ,further comprising: a first tunnel junction positioned between the topreflector and the active region.
 80. The device of claim 67 , whereinthe active region includes at least a first quantum well.
 81. The deviceof claim 67 , wherein the active region includes a plurality of quantumwells.
 82. The device of claim 81 , wherein at least a portion of theplurality of first quantum wells have different maximum gain wavelength.83. The device of claim 67 , wherein the active region includes at leasta first bulk region.
 84. An optical system, comprising: a die includinga top surface and a plurality of layers, at least one of the layersbeing an oxide layer formed of an oxidizable material that is oxidizedupon exposure to an oxidizing agent to convert the oxidizable materialto an electrical insulator, the die including a plurality of oxideapertures connecting the top surface to the oxide layer, a majority ofindividual oxide apertures having different sizes; a tunable laserformed in one of the oxide apertures, the laser including an activeregion with first and second opposing reflectors that define a lasergain cavity; a first photodetector positioned outside of the laser gaincavity; and an adjustable wavelength selective filter that splits theoutput beam into a transmitted portion and a reflected portion, theadjustable wavelength selective filter being positioned at an angle 0relative to the optical axis to provide an angular dependence of awavelength reflection of the wavelength selective filter and direct thereflected output beam towards the first photodetector, wherein thewavelength selective filter provides wavelength selectivity by changingthe angle θ and a ratio of the transmitted and reflected portions is afunction of wavelength of output beam and the angle
 0. 85. The system ofclaim 84 , wherein the plurality includes at least three oxideapertures.
 86. The system of claim 84 , wherein the plurality includesat least four oxide apertures.
 87. The system of claim 84 , wherein eachof an individual oxide aperture in the plurality has a different pitch.88. The device of claim 84 , wherein the plurality of oxide aperturesare formed by via holes connecting the top surface to the oxide layer.89. The device of claim 84 , wherein the plurality of oxide aperturesare formed by trench structures connecting the top surface to the oxidelayer.
 90. The device of claim 84 , wherein the plurality of oxideapertures are formed by mesas connecting the top surface to the oxidelayer.
 91. The system of claim 84 , wherein the tunable laser is a VCSELlaser.